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MP1048 full bridge ccfl controller MP1048 rev. 0.9 www.monolithicpower.com 1 9/24/2007 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2007 mps. all rights reserved. the future of analog ic technology description the MP1048 is a fixed operating frequency inverter controller that controls four external n-channel power mosfets in a full-bridge configuration. the inverter is designed to power up to 6 cold cathode fluorescent lamps (ccfls) to backlight liquid crystal displays. its full-bridge architecture converts unregulated dc input voltages to the nearly pure sine waves required to ignite and operate ccfls. for reliable lamp ignition, the operating frequency is set by an external resistor and during startup is temporarily swept toward the unloaded resonant frequency of the tank. burst mode or analog mode dimming are controlled with an external analog signal. built-in fault management features include an open lamp regulator, a transformer secondary peak current regulator and a dual-mode fault timer. the secondary over-current timeout can be shortened with external components. the MP1048 is available in tssop28 and soic28 packages. features ? capable of driving up to 6 lamps ? controls four external, low cost, n-channel mosfets ? fixed operating frequency ? input voltage range of 10v to 22v ? lamp current and voltage regulation ? full-wave sense amp ? analog and burst mode dimming control ? integrated burst mode os cillator and modulator ? soft-on and soft-off burst envelope ? open lamp protection ? secondary over-current protection ? dual-mode fault timer ? available in tssop28 and soic28 packages applications ? desktop lcd flat panel displays ? monitors ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. the MP1048 is covered by us pat ents 6,683,422, 6,316, 881, and 6,114,814. other patents pending. typical application MP1048 si li lv comp ag ft lcs lcc brc brs dbrt abrt en nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pgl lgl vccl outl ugl btl prl pgr lgr vccr outr ugr btr prr gnd v ps dbrt abrt en www.datasheet.co.kr datasheet pdf - http://www..net/
MP1048 ? full bridge ccfl controller MP1048 rev. 0.9 www.monolithicpower.com 2 9/24/2007 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2007 mps. all rights reserved. package reference part number* package temperature MP1048em tssop28 ?20 c to +85 c MP1048ey soic28 ?20 c to +85 c * for tape & reel, add suffix ?z (eg. MP1048em?z) for rohs compliant packaging, add suffix ?lf (eg. MP1048em?lf?z) absolute maxi mum ratings (1) input voltage v prr, v prl ............................... 24v logic inputs ................................ ?0.3v to +6.5v inputs si, li, lv ................................ ?5v to +5v junction temperature...............................150 c power dissipation...................................... 0.6w junction temperature...............................150 c lead temperature (solder) ......................260 c operating frequency............................. 150khz storage temperature ..............?55 c to +150 c recommended operating conditions (2) input voltage v prr, v prl .................... 10v to 22v analog brightness voltage v abrt ....... 0v to 1.2v digital brightness voltage v dbrt ........ 0v to 1.2v enable voltage v en ............................ 0v to 5.0v operating frequency............. 20khz to 100khz operating frequency (typical) ................ 60khz operating temperature .............?20 c to +85 c thermal resistance (3) ja jc tssop28 ............................... 82 ...... 20... c/w soic28................................... 60 ...... 30... c/w notes: 1) the device is not guaranteed to function outside of its operating conditions. 2) exceeding these ratings may damage the device. 3) measured on approximately 1? square of 1 oz copper. electrical characteristics v prr = v prl = 17.5v, v brc = v lcc = gnd, t a = +25 c, unless otherwise noted. parameter symbol condition min typ max units output gate pull-down r gd 2.0 ? gate pull-up r gu 20 ? damper on resistance r on 1.2 k ? en threshold v th 1.2 2.0 v hysteresis v th_hys 0.3 v sync timing dbrt logic input threshold v th v brs = v cc 1.8 2.0 2.3 v dbrt logic input hysteresis v th_hys v brs = v cc 0.2 v burst rate generator source current i src(brs) v brs = 2v 125 150 175 a lower threshold v v(brs) 2.2 2.35 2.5 v upper threshold v p(brs) 3.2 3.4 3.6 v si li lv comp ag ft lcs lcc brc brs dbrt abrt en n/c pgl lgl vccl outl ugl btl prl pgr lgr vccr outr ugr btr prr 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 top view www.datasheet.co.kr datasheet pdf - http://www..net/
MP1048 ? full bridge ccfl controller MP1048 rev. 0.9 www.monolithicpower.com 3 9/24/2007 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2007 mps. all rights reserved. electrical characteristics (continued) v prr = v prl = 17.5v, v brc = v lcc = gnd, t a = +25 c, unless otherwise noted. parameter symbol condition min typ max units supply current supply current (enabled) i pr 2.2 3 ma supply current (disabled) i pr 3 25 a operating frequency f 0 r3 = 100k ? 45 49 53 khz accuracy of f 0 3 8 % frequency set voltage v lcs 1.13 1.18 1.23 v lamp current feedback v abrt > 1.2v 1.134 1.20 1.266 magnitude |v li | v abrt = 0v 0.35 0.40 0.45 v accuracy v li 3 % input resistance r li v li < 0v 60 k ? open lamp voltage feedback threshold (peak) v th(lv) 1.15 1.20 1.25 v secondary peak current threshold v th(si) 1.15 1.20 1.25 v fault timer threshold v t(ft) 1.15 1.20 1.25 v sink current i sink(ft) ? 1 a open lamp source current i so(ft)+ 1 a secondary over-current source current i sp(ft)+ 65 a comp clamp voltage v comp 0.62 v reference current i comp+ 20 a decay current i comp- end of burst 20 a output (vccr and vccl) voltage v cc 5.7 6.0 6.3 v current i cc 5 ma www.datasheet.co.kr datasheet pdf - http://www..net/
MP1048 ? full bridge ccfl controller MP1048 rev. 0.9 www.monolithicpower.com 4 9/24/2007 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2007 mps. all rights reserved. pin functions pin # name description 1 si secondary current feedback input. connect a current sense resistor from the cold end of the secondary winding to ground. connect this pin to the junction of the resistor and the secondary winding. if the voltage at si exceeds +1.2v, a pulse of current will pull down on the comp pin in an attempt to regulate the secondary curr ent and the fault timer will be started. 2 li lamp current feedback input. connect this pin to the cold end of the lamp and shunt a sense resistor to ground. the sense amplifier will sink a current from the comp pin that is proportional to the absolute value of the voltage at this pin. (in regulation the average of the absolute value of the voltage at this pin is determined by the voltage at the abrt pin). 3 lv lamp voltage feedback input. connect a capacitive voltage divider from the hot end of the lamp to ground. connect this pin to the tap on the divider and shunt a bias resistor to ground. if the voltage at lv exceeds +1.2v, a pulse of current will pull down on the comp pin to attempt to regulate the lamp voltage and the fault timer will be started. 4 comp feedback compensation node. connect a compensation capacitor from this pin to ground. 5 ag analog ground. 6 ft fault timing. connect a timing capacitor from this pin to ag to set the fault timeout period. 7 lcs lamp operating clock set. connect a resistor from this pin to ag. this resistor sets the operating frequency of the MP1048. 8 lcc lamp clock control. lcc provides compensation when the operating clock is swept in order to strike the lamp. connect a resistor in series with a capacitor from lcc to ag. connect a smaller capacitor directly from lcc to ag. connect only a single capacitor to ag, if some sweeping of the operating clock can be tolerated during open lamp conditions. connect lcc to ag to force the operating clock to the selected value at all times. 9 brc burst repetition rate control. connect brc to ag. 10 brs burst repetition rate setting. if the burst repetition rate is to be synchronized to an external clock, connect a capacitor from brs to ag. if the burst rate generator is free-run and will not be synchronized with an external clock, connect a resistor in parallel with a capacitor from brs to ag. if the burst is to be controlled by an extern al logic signal, connect brs to vcc and apply the logic signal to the dbrt pin. 11 dbrt burst-mode (digital) brightness control input. the voltage range of 0v to 1.2v at dbrt linearly sets the burst-mode duty cycle from minimum 10% to 100%. if burst dimming is not used, tie dbrt to vcc. 12 abrt analog brightness control input. the voltage range of 0v to 1.2v at abrt sets the 3:1 dimming range for the lamp current. if analog dimming is not used, tie abrt to vcc. 13 en enable input. pull en high to turn on the MP1048; low to turn it off. 14 nc no connect. 15 prr input power rail, right-side. connect prr directly to the drain of the high-side, right-side, external power mosfet. 16 btr output bootstrap, right-si de. btr provides gate bias for the right-side high-side mosfet. connect a capacitor from btr to outr. 17 ugr high-side mosfet gate output, right-side. connect ugr to the gate of the high-side, right-side, external power mosfet. 18 outr bridge output, right-side. connect outr to the source of the right-side, high-side mosfet and the drain of the low-side, right-side mosfet. 19 vccr voltage rail output, right-side. vccr a llows bypassing the bias supply for the control circuitry. bypass vccr with a 0.47f capacitor. connect to vccl. www.datasheet.co.kr datasheet pdf - http://www..net/
MP1048 ? full bridge ccfl controller MP1048 rev. 0.9 www.monolithicpower.com 5 9/24/2007 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2007 mps. all rights reserved. pin functions (continued) pin # name description 20 lgr low-side mosfet gate output, right-side. connect lgr to the gate of the low-side, right side mosfet. 21 pgr power ground, right-side. connect pgr to t he source of the low-side, right-side mosfet. 22 prl input power rail, left-side. connect prl dire ctly to the drain of the high-side, left-side, external power mosfet. 23 btl output bootstrap, left-side. btl provides gate bias for the left-side high-side mosfet. connect a capacitor from btl to outl. 24 ugl high-side mosfet gate output, left-side. connect ugl to the gate of the high-side, left side, external power mosfet. 25 outl bridge output, left-side. connect outl to the source of the left-side, high-side mosfet and the drain of the left-side, low-side mosfet. 26 vccl voltage rail output, left-side. vccl a llows bypassing the bias supply for the control circuitry. bypass vccl with a 0. 47f capacitor. connect to vccr. 27 lgl low-side mosfet gate output, left-side. connect lgl to the gate of the low-side, left side mosfet. 28 pgl power ground, left-side. connect pgl to the source of the low-side, left-side mosfet. www.datasheet.co.kr datasheet pdf - http://www..net/
MP1048 ? full bridge ccfl controller MP1048 rev. 0.9 www.monolithicpower.com 6 9/24/2007 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2007 mps. all rights reserved. operation fault management error amp lamp clock v ps v ccr pwm control logic r8 r li 1.2v r2 c2 c1 r3 r4 r6 c4 r1 1.2v 1 3 6 2 12 4 7 8 10 9 13 11 5 si lv ft li li abrt comp lcs lcc brs brc en dbrt ag burst rate generator burst pwm level shift level shift c3 r7 c7 c10 c12 r9 v ps v ps si lv li c8 c11 c13 c14 c9 22 24 23 25 27 28 26 15 17 16 18 20 21 19 prl ugl btl outl lgl pgl vccl prr ugr btr outr lgr pgr vccr figure 1?functional block diagram design information the MP1048 is a fixed operating frequency inverter controller specifically designed to drive up to 6 cold cathode fluorescent lamps (ccfls) used as a backlight for liquid crystal displays. designed to run off 10v to 22v input supplies, the MP1048 can drive up to 6 lamps via four (4) external n-channel mosfets. its full bridge architecture converts unregulated dc input voltages to the nearly pure sine waves required to ignite and operate ccfls. the operating frequency is set by an external resistor to minimize the possibility of interference with the refresh rate of the display. to ensure ignition of the lamp, the operating frequency is swept temporarily to the unloaded resonant frequency of the tank. regulated lamp current and maximum peak transformer secondary current are set by external resistors. regulated open lamp voltage is set by an external capacitive voltage divider. soft startup of the lamp minimizes the peak transformer secondary voltage. the MP1048 implements burst mode dimming of the lamp and features soft-on/soft-off control of the lamp current envelope that is virtually independent of supply voltage. burst repetition rate and duty cycle can either be determined by driving the MP1048 with an external logic signal or by choosing an external resistor and capacitor to set the burst rate and modulating the duty cycle with a dc control voltage on d brt . loop gain is compensated for variations in supply voltage and the full-wave lamp current sense amplifier provides superior output pulse symmetry, loop response time and phase margin. www.datasheet.co.kr datasheet pdf - http://www..net/
MP1048 ? full bridge ccfl controller MP1048 rev. 0.9 www.monolithicpower.com 7 9/24/2007 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2007 mps. all rights reserved. careful management of limit conditions provides graceful reduction of lamp power at low supply voltages but allows the loop to recover quickly from an abrupt step in supply voltage. system fault management facilities include an on-chip open-lamp regulator, a transformer secondary peak current regulator and a dual-mode fault timer. by regulating the peak current in the transformer secondary winding, ul1950 can be met for most systems. when the MP1048 is regulating open lamp voltage, it ignores the burst control and runs continuously to ensure either the lamp has a chance to re-ignite or the fault timer can smoothly and accurately time out. if the MP1048 detects an open lamp condition for a time that exceeds the timer interval, it will shutdown until the part is turned off and then turned on again. similarly, the MP1048 will shutdown if it detects an over-current condition in the secondary for about 2% of the open lamp timer interval. if required, the secondary over-current timeout can be shortened with external components. on-chip current limit protects the MP1048 in case of output fault conditions. feature description all reference designators refer to the MP1048 block diagram, unless otherwise designated. high efficiency operation there are two major power losses in a ccfl inverter: switching loss of switches and copper loss of the transformer winding. to reduce switching loss, zero current switching (zcs as described in us patent 6,114,814) or zero voltage switching (zvs) are commonly implemented. as shown in figure 2, zcs and zvs require primary current i pri lagging primary voltage v pri . with zvs, since d1 can only conduct at the negative phase of i pri , the beginning of a & d conduction will only happen at the negative phase of i pri . higher phase delay will lead to higher primary rms current and therefore higher transformer temperature. with zcs, a & d conduction starts at the zero crossing of i pri . the MP1048 does not utilize zvs or zcs. it implements fast switching to reduce switching loss and operates at the condition that i pri and v pri are in phase to reduce primary rms current. therefore, higher efficiency than zvs or zcs is achieved. a d1 b + v ps i pri v pri c d - v ps v pri : i pri : zvs zcs MP1048 0 0 0 a,d b,c figure 2?v pri vs. i pri brightness control the MP1048 can operate in four modes: analog mode, burst mode with a dc input, burst mode with an external pwm or analog and burst mode. the four modes are dependent on the pin connections defined under pin functions. choosing the required burst repetition frequency can be achieved by an rc combination as defined in component selection. the MP1048 has a soft-on and soft-off feature to reduce noise when using burst mode dimming. analog dimming and burst dimming are independent of each other and may be used together to obtain a wider dimming range. www.datasheet.co.kr datasheet pdf - http://www..net/
MP1048 ? full bridge ccfl controller MP1048 rev. 0.9 www.monolithicpower.com 8 9/24/2007 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2007 mps. all rights reserved. table 1?function modes pin connection function abrt dbrt brs ratio analog mode 0 ? 1.2v v cc v cc 3:1 burst mode with dc input voltage v cc 0 ? 1.2v r6 c7 10:1 burst mode with external source v cc pwm v cc set by customer analog and burst mode 0 ? 1.2v 0 ? 1.2v r6 c7 30:1 analog and burst mode with external source 0 ? 1.2v pwm v cc set by customer brightness polarity burst: 100% duty cycle is at 1.2v analog: 1.2v is for maximum brightness fault protection open lamp: the lv pin (#3) is used to detect whether an open lamp condition has occurred. if the voltage at lv exceeds +1.2v, a pulse of current will pull down on the comp pin to regulate the lamp voltage. the fault timer will be started with a 1a current source injecting into c2 at the ft pin, while the fault condition persists. if the voltage at the ft pin exceeds 1.2v, then the chip will shutdown. excessive secondary current (shorted lamp) : the si pin (#1) is used to detect whether excessive secondary current has occurred. if a fault condition occurs that increases the secondary current, then the voltage at si will be greater than 1.2v. a pulse of current will pull down on the comp pin to regulate the secondary current. the fault timer will be started with a 65a current source injecting into c2 at the ft pin while the fault condition persists. if the voltage at the ft pin exceeds 1.2v, then the chip will shutdown and need to be enabled again. fault timer : the timing for the fault timer will depend on the sourcing current as described above and the capacitor c2 on the ft pin. the user can program the time for the voltage to rise after the chip detects a ?real? fault. when a fault is triggered, the internal voltage (v cc ) will collapse from 6v to 0v. if no fault is detected a 1a current sink will keep ft to 0v. startup for reliable ignition of the lamp, the operating frequency is swept temporarily toward the unloaded resonant frequency of the tank during startup. this guarantees the strike voltage of the lamp at any temperature due to a resonant topology for switching the outputs and eliminates the need for external ramp timing circuits to ensure startup. once the strike voltage is achieved, the switching frequency is gradually adjusted to the preset fixed value. the operating frequency before the lamp strikes can be swept as much as 160% of the preset frequency value. chip enable the chip has an on/off function, which is controlled by the en pin (#13). the enable signal goes directly to a schmitt trigger. the chip will turn on with an en = high and off with an en = low. www.datasheet.co.kr datasheet pdf - http://www..net/
MP1048 ? full bridge ccfl controller MP1048 rev. 0.9 www.monolithicpower.com 9 9/24/2007 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2007 mps. all rights reserved. application information pin 1 (si), r1: secondary short protection: r1 is used for feedback to the si pin to detect excessive secondary current. the value for r1 is calculated as 1.2v divided by the secondary peak current. pin 2 (lv): c13, c14 and r8: open lamp protection: the regulated open lamp voltage is proportional to the c14 and c13 ratio. c13 has to be rated at 3kv and is typically between 5pf to 22pf. the value of c14 is set by the customer to achieve the required open lamp voltage detection value. () rms v 18 . 1 13 c 14 c max = the value of bias resistor r8 is typically 100k ? (not critical). pin 2 (li), r2: lamp current regulation: r2 is used for feedback to the li pin to regulate the lamp current. the value for r2 is calculated as 1.33v divided by the lamp rms current (assuming v abrt is greater than 1.2v). for a rms 6ma lamp current, the r2 value is 220 ? . pin 6 (ft), c2: c2 is used to set the fault timer. this capacitor will determine when the chip will reach the fault threshold value. open lamp time out: () v 2 . 1 a 1 t nf 2 c lamp open = for c2 = 820nf, then the timeout for open lamp will be 0.98 sec. secondary over current timeout : when the MP1048 is regulating secondary over current (si feedback), the source current in the fault timer (ft) cap is approximately 65a. this causes the si timeout to be about 1/65 of the open lamp (lv) timeout. to reduce the si timeout further, modify the network at the ft pin as shown in figure 3. ft c2a c2b figure 3?timeout adjustment for a c2b = 10nf, then the time out for secondary short will be 0.2ms. note: the open lamp time out will remain the same value as defined by c2a. pin 7 (lcs), r3: r3 is used to set the lamp operating clock. the value for r3 is calculated by = f e 5 3 r 9 for r3 = 100k ? , operating clock will be 50khz. pin 8 (lcc): this is the lamp clock control compensation pin and needs a lag lead lag capacitor/resistor network. pin 4 (comp), c1: c1 is the feedback compensation capacitor that connects between comp and ag. a 1.5nf or 2.2nf cap is recommended. this cap should be x7r ceramic. the value of c1 affects the soft-on rise time and soft-off fall time. pin 18 (outr), pin 25 (outl), c12, r9: the outr and outl pins are used to sense the voltage at the output of the full bridge. they are also the point of access for the output dampers. outr and outl should make a kelvin connection to the sources of the high-side mosfets and the drains of the low-side mosfets in the output bridge. the primary transformer current flows through capacitor c12. its value is typically 2.2f. this capacitor should be ceramic and has a ripple current rating greater than the primary current. it is more optimal to use two parallel 1f ceramic caps for minimal esr losses. r9 is used to ensure that the bridge outputs are at 0v prior to startup. typically r9 = 300 ? to 3k ? . www.datasheet.co.kr datasheet pdf - http://www..net/
MP1048 ? full bridge ccfl controller MP1048 rev. 0.9 www.monolithicpower.com 10 9/24/2007 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2007 mps. all rights reserved. pin 16 (btr), pin 23 (btl), c8, c10: btr and btl are the bias supplies for the level shift of the upper mosfets. c8 and c10 should be 22nf and made of x7r ceramic material. pin 19 (vccr), pin 26 (vccl), c9, c11: these capacitors bypass the gate supply for the low-side switches. they also supply power to the MP1048. these pins should be bypassed with a 0.47f ceramic x7r capacitor. important?for all applications, vccr and vccl must be connected together. pin 11 (dbrt): this pin is used for burst brightness control. the dc voltage on this pin will control the burst percentage on the output. the signal is filtered for optimal operation. a voltage ranging from 0v to 1.2v on dbrt will correspond to a burst duty cycle of the minimum to 100% respectively. for direct pulse width modulation of the burst signal, connect brs to vcc and connect dbrt with a logic level pwm signal. a logic high is burst on and a logic low is burst off. pin 10 (brs): c7, r6: brs is used to set the burst repetition rate. c7 and r6 will set the burst repetition rate and the minimum burst time: t min. set t min to achieve the minimum required system brightness. ensure that t min is long enough that the lamp does not extinguish. these values are determined as follows: select a minimum duty cycle, d min , where: burst min min f t d = () rise fall fall min t t t d + = if operating in free-running mode: b v p min i 2 v v vbg 1 d 1 6 r + + ? ? ? ? ? ? ? ? ? = k 43 . 21 1 d 1 k 16 . 21 ~ 6 r min + ? ? ? ? ? ? ? ? ? for d min =0.1 and r6=212k ? ? = 6 r f d 1 7 c b min for d min =0.1, r6=212k, f b =200hz, then c7=52nf: where d min =minimum burst duty cycle, vbg=v p - v v (~1.2v), v p =peak brs voltage (~3.6v), v v = valley brs voltage (~2.4v) and f b =burst repetition rate. 405 . 0 4 . 2 6 . 3 ln ? ? ? ? ? ? = esd resistor it is recommended that a resistor (r li = 1k ? ) be added in series with the lamp current feedback as shown in figure 4. the addition of this resistor helps minimize the possibility of esd damage in case of mishandling of the ic during board level assembly and test. MP1048 li figure 4?esd resistor www.datasheet.co.kr datasheet pdf - http://www..net/
MP1048 ? full bridge ccfl controller MP1048 rev. 0.9 www.monolithicpower.com 11 9/24/2007 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2007 mps. all rights reserved. package information tssop28 0.19 0.30 9.60 9.80 seating plane 0.65 bsc pin 1 id 4.30 4.50 6.20 6.60 1 14 15 28 0.80 1.05 1.20 max 0.05 0.15 top view front view side view 0.09 0.20 see detail "a" recommended land pattern 5.80 typ 1.60 typ 0.40 typ 0.65 bsc detail a 0.45 0.75 0 o -8 o 0.25 bsc gauge plane note: 1) all dimensions are in millimeters. 2) package length does not include mold flash, protrusion or gate burr. 3) package width does not include interlead flash or protrusion. 4) lead coplanarity (bottom of leads after forming) shall be 0.10 millimeters max. 5) drawing conforms to jedec mo-153, variation ae. 6) drawing is not to scale. www.datasheet.co.kr datasheet pdf - http://www..net/
MP1048 ? full bridge ccfl controller notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. MP1048 rev. 0.9 www.monolithicpower.com 12 9/24/2007 mps proprietary information. unaut horized photocopy and duplication prohibited. ? 2007 mps. all rights reserved. soic28 note: 1) control dimension is in inches. dimension in bracket is in millimeters. 2) package length does not include mold flash, protrusions or gate burrs. 3) package width does not include interlead flash or protrusions. 4) lead coplanarity (bottom of leads after forming) shall be 0.10 millimeters max. 5) drawing conforms to jedec ms-013, variation ae. 6) drawing is not to scale. 0.013(0.33) 0.020(0.51) 0.697(17.70) 0.713(18.10) seating plane 0.050(1.27) bsc pin 1 id 0.291 (7.40) 0.299 (7.60) 0.394 (10.00) 0.418 (10.60) 1 14 15 28 0.093(2.35) 0.104(2.65) 0.004(0.10) 0.012(0.30) top view front view side view 0.009(0.23) 0.013(0.33) recommended land pattern 0.370 (9.40) 0.079 (2.00) 0.024 (0.61) 0.050 (1.27) see detail "a" 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.030(0.75) x 45 o 0.010(0.25) bsc gauge plane www.datasheet.co.kr datasheet pdf - http://www..net/

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